With better downsizing potentiality and smaller power consumption than CRTs (Cathode Ray Tubes), liquid crystal display apparatuses are widely used not only for mobile electronic devices but also for stationary electronic devices such as personal computers. In particular, active matrix liquid crystal display apparatuses, in which a switching element is provided in each of pixel display sections in a display panel, excel in good contrast by nature and potentiality to increase the speed of response, and hence the active matrix liquid crystal display apparatuses have been widely used in recent years.
As the switching elements of those active matrix liquid crystal display apparatuses, along with non-linear resistive elements and semiconductor elements, thin film transistors (hereinafter, will be referred to as TFT) formed on a transparent insulating substrate have widely been adopted, since they can realize transmissive displaying and can be easily enlarged.
Among the different types of TFTs, TFTs in which a semiconductor layer of a channel part is made of polycrystalline silicon (p-Si) consume lower electric power and can speedily respond, compared to conventional TFTs using amorphous silicon (a-Si). Since the TFTs using p-Si realizes speedy response, a liquid crystal drive circuit can be fabricated by providing the TFTs using p-Si on the periphery of a liquid crystal display apparatus. In this way, it is possible to utilize the TFTs using p-Si for a monolithic process by which a display section and a drive circuit section are integrally formed on a single substrate. Liquid crystal display apparatuses in which this integral formation is realized are called driver-monolithic liquid crystal display apparatuses.
The following description will discuss an arrangement of a driver-monolithic liquid crystal display apparatus including driver circuits, with reference to FIGS. 7 and 8.
FIG. 7 is a schematic diagram illustrating a conventional display apparatus. The display apparatus of FIG. 7 is provided with: a display section 100 (including a plurality of pixel TFTs and a plurality of pixel display sections which are both provided in a matrix manner, a plurality of signal lines, plurality of scanning lines both connected to the pixel TFTs and the pixel display sections, the signal lines intersecting with the scanning lines in an orthogonal manner); a signal line drive circuit 200; a scanning line drive circuit 300 for supplying desired video signals to the desired pixel display sections via the signal lines and the scanning lines connected to the pixel TFTs; and, video lines 400 for supplying the video signals.
FIG. 8 is a schematic diagram illustrating the arrangement of the display section 100 in detail. The display section 100 of FIG. 8 is provided with: a signal line group 120 composed of a plurality of signal lines; a scanning line group 110 composed of a plurality of scanning lines; and pixel TFTs 130. The pixel TFTs 130 correspond to the respective intersections of the signal lines of the group 120 and the scanning lines of the group 110, and each of the pixel TFTs 130 is arranged in such a manner that a gate terminal is connected to a scanning line, either one of a source terminal and a drain terminal is connected to a signal line, and the other is connected to a pixel display section. For instance, in the pixel TFT 130 in FIG. 8, a gate terminal 131 is connected to a scanning line 111, a source terminal 132 is connected to a signal line 121, and a drain terminal 133 is connected to a pixel display section 140.
In FIG. 8, an electric potential is supplied via the scanning line 111. The pixel TFT 130 functions as a switching element for electrically connecting a pixel electrode included in the pixel display section to the signal line 121.
Moreover, the signal line drive circuit 200 supplies the video signals, which have been supplied via the video lines 400, to the desired signal lines.
Further, the scanning line drive circuit 300 applies a voltage, which is either for turning the pixel TFTs ON (in this case, the voltage will be referred to as scanning line select voltage) or for turning the pixel TFTs OFF (in this case, the voltage will be referred to a scanning line non-select voltage), to the desired scanning lines in each horizontal period.
In this arrangement, the optical transmittance of a liquid crystal layer between a pixel electrode and an opposing electrode of the pixel display section is controlled by applying a voltage which is equivalent to a desired video signal to the layer between the pixel electrode and the opposing electrode, so that desired pixel display is carried out.
A liquid crystal display apparatus as described above is just one example of apparatus which uses a pixel TFT. Display apparatuses such as active matrix EL (Electro Luminescence) display apparatuses also include pixel TFTs, and hence also in these display apparatuses, video signals are supplied to pixel display sections via respective pixel TFTs. For this reason, the foregoing description is applicable to driver-monolithic display apparatuses in general.
FIG. 10 shows an arrangement of a projection apparatus including a liquid crystal display apparatus. The projection apparatus in FIG. 10 includes liquid crystal panels 601, 602, and 603 corresponding to respective colors of R, G, and B, so as to be a so-called three-panel type liquid crystal projection apparatus. The projection apparatus is arranged in such a manner that after separating a light beam emitted from a lamp 614 such as a UHP lamp (high-pressure mercury pump) into R, G, and B using a dichroic mirror 605, the beams of R, G, and B enter the respective liquid crystal panels 601-603, and then the beams of R, G, and B are re-united by a cross prism 606 so as to be projected on a screen using a projection lens 607. To put it another way, each of the liquid crystal panels 601-603, which functions as a filter allowing a monochromatic light beam which is R, G, or B to pass through, facilitates tonal displaying including halftones by controlling the optical transmittance, so as to realize full-color displaying by synthesizing tones obtained in each colors of R, G, and B.
Display apparatuses with higher resolution have been demanded in recent years, and since the time allocated for one pixel on the occasion of carrying out refreshing with a constant frequency has become shorter as the number of pixels used for displaying increases, it has been required to speedily sample video signals. For instance, as the dot clock frequency is 65 MHz in the case of XGA (1024×768) resolution and 74.34 MHz in the case of DTV (1280×720) resolution, simple mathematics demonstrate that the time allocated for one pixel is no more than 10-15 nsec. Moreover, when double-speed driving is carried out in order to restrain the flicker of displaying, the time allocated for the sampling is halved.
A method (so-called a method of multipoint simultaneous sampling) which has conventionally been used for responding to this requirement of high-speed sampling is arranged such that a sufficient sampling period is secured by serial-parallel converting of the video signals for some pixels, using an IC provided outside of the substrate. Using this method, it is possible to set the sampling period to be, for instance, 6 times longer on the occasion of 6-point simultaneous sampling and 12 times longer on the occasion of 12-point simultaneous sampling, compared to conventional sampling.
FIG. 9 shows an internal arrangement of a signal line drive circuit which uses a multipoint simultaneous sampling method as described below.
The signal line drive circuit in FIG. 9 is provided with a shift register circuit 210 and a sampling circuit 230. Sampling pulse signals which are progressively outputted from the shift register circuit 210 are supplied to the gates of an analog switch group 240 which is provided in the sampling circuit 230 and composed of a plurality of analog switches for sampling. In accordance with the signals supplied to the gates, the analog switch group 240 connects one of lines 401-403 which constitute a video line group 400 to a desired signal line. That is to say, the analog switch group 240 is turned ON when the sampling pulse signals are supplied, so as to sample the video signals. These video signals are supplied to signal lines via the analog switch group 240, and eventually reaches the desired pixel.
The signal line drive circuit in FIG. 9 shows an example of 3-point simultaneous sampling by which a sampling pulse signal outputted from the shift register circuit 210 is branched off and then inputted simultaneously to, for instance, analog switches 241-243 for sampling. In short, in the foregoing example, the analog switches 241-243 are simultaneously operated by the sampling pulse signals.
After being inputted via the video lines 401-403, the video signals are supplied to the analog switches 241-243 via connecting lines 251-253 provided so as to intersect with the video lines 401-403. In this arrangement, it is ideal that the total resistances (the amounts of the delay of the video signals) of respective three pathways for supplying the video signals from input terminals to the analog switches via three video lines are identical with each other. This is because the non-uniformity of luminance looking like lines is identified on the occasion of displaying, unless the video signals, which are supplied via three pathways and to be simultaneously sampled, are equally transmitted.
For instance, liquid crystal display apparatuses receive a signal with oscillation around 4-5V as a video signal, and when 128 tones are realized as analog levels, the deviation of tones is caused by only a dozen mV of voltage fluctuation. Thus, to improve the display quality, it is essential to equalize the electrical characteristics of the pathways for transmitting video signals and to supply the signals uniformly. In other words, it is necessary to eliminate the difference (of the delay of) the video signals which is caused in connecting lines, to improve the display quality.
There are known conventional arts for eliminating this difference of the delay of video signals between connecting lines, such as a patent document 1 (Japanese Laid-Open Patent Application No. 7-175038/1995 (Tokukaihei 7-175038; published on Jul. 14, 1995)), a patent document 2 (Japanese Laid-Open Patent Application No. 7-319428/1995 (Tokukaihei 7-319428; published on Dec. 8, 1995), and a patent document 3 (Japanese Laid-Open Patent Application No. 9-325370/1997 (Tokukaihei 9-325370; published on Dec. 16, 1997).
According to these patent documents, the following measures are taken to equalize the electrical characteristics of the pathways for transmitting video signals and to compensate the difference of the delay of video signals between connecting lines.
That is to say, according to the patent document 1, the location of a contact hole for connecting analog switches to connecting lines branched from video lines is moved by the distance between the video lines, in order to equalize the resistances of respective connecting lines.
According to the patent document 2, connecting lines branched from video lines are formed by respective p-Si films to each of which a different amount of N-type impurity ion is injected, in order to equalize the resistances of the respective connecting lines.
Moreover, according to the patent document 3, the widths or the lengths of connecting lines branched from video lines are adjusted in order to substantially equalize the resistances of the respective connecting lines.
Incidentally, the downsizing and the improvement of resolution of display apparatuses such as liquid crystal display apparatuses have recently been required.
However, the techniques disclosed by the foregoing patent documents (hereinafter, these techniques will be referred to as conventional techniques) focus on the adjustment of the resistances of connecting lines branched from video lines or the resistances of the contact sections between the connecting lines and analog switches for sampling.
Thus, the conventional techniques have such problems that the design flexibility is significantly limited and the resistances of the connecting lines or the resistances of the contact sections between the connecting lines and the analog switches could be increased.
The following is the detailed description of these problems.
When a plurality of connecting lines are provided so as to intersect with a plurality of video lines, in order to avoid a connecting line to be short-circuited with video lines other than the video line which should be connected to the connecting line, it is necessary that the video lines are formed on a layer different from a layer on which the connecting lines are formed, and the video lines are selectively connected to the connecting lines.
Being required to have low resistance, the video lines are made of metals with low resistance such as aluminum. In the meantime, the connecting lines from the video lines to the analog switches are often made of materials with high resistance. For instance, to simplify the fabricating process, it is effective to adopt a material identical with the material of a gate electrode, such as a polycrystalline silicon thin film, to the connecting lines.
However, since the sheet resistance of the polycrystalline silicon thin film is a dozen times higher than the resistance of the metal with low resistance which is used for the video lines and also the resistance of a connecting line connecting the video line and the sampling circuit is significantly varied in accordance with the distance from the video line to the sampling circuit, it is necessary to tailor the layout of each connecting line to equalize the resistances of all connecting lines.
In particular, in the case of high-resolution display apparatuses with not more than 20 μm pixel spacing, since the foregoing conventional arts are all arranged so as to increase the resistances of signal pathways to be equal to the signal pathway with the highest resistance, the design flexibility is restrained and this could cause the increase of the resistances in totality, which is a fatal drawback to the demand of high-speed sampling.
As a result, the display quality of the high-resolution display apparatuses with not more than 20 μm line spacing is deteriorated because, since each of the pathways for supplying video signals has different resistance, the video signals are supplied at different speeds and hence the non-uniformity of luminance (non-uniformity of displaying), which looks like lines, is identified on the occasion of displaying.
Moreover, in order to downsize the projection apparatus in FIG. 10, it is required not only to downsize the liquid crystal display apparatus but also to improve the resolution thereof. However, since conventional liquid crystal display apparatuses are not suitable for downsizing and the improvement of resolution, there has been a limit for the downsizing and the improvement of resolution of the projection apparatus, when a conventional liquid crystal display apparatus is adopted.